JTAG Boundary Scan Test Systems (IEEE 1149.1)

News Articles - 2007

The potential of boundary scan
Electronics Weekly – November 2007

Debug and test techniques must advance in parallel with new design approaches being applied at component and board levels. Boundary scan testing presents an answer to the progressive designing-out of test access. It also has the ability to establish a deterministic test duration for a board, for all stages of the product lifecycle. Boundary scan test equipment with graphical user interfaces has allowed engineers to access more of this technology’s potential. Full article    (PDF, 340k)

All for one. How the latest JTAG interfaces can be a useful ally in the fight to cut development time
New Electronics – November 2007

XJTAG Version 2.0, the company’s latest brainchild aims to give customers an ‘all in one’ boundary scan system that enables them to get their boards up and running in minutes and hours, not days and weeks as is the case with some traditional systems. The point being made here is that in today’s ‘right first time’ environment, developers increasingly need a test solution that not only maximises test coverage when it come to manufacture, but minimises board debug time in order to get their designs to market quickly. XJTAG says it now provides a common platform that can be shared by ‘one and all’ during the design and development of the product lifecycle. Full article    (PDF, 264k)

Using boundary scan to preserve board-level IP
Electronics magazine – October 2007

Boundary scan testing creates a test infrastructure that is inherently suited to preserving and re-using test knowledge throughout the product lifecycle. It provides a convenient means for original equipment manufacturers, design houses, test specialists and electronic manufacturing services ( EMS ) providers to maximize the value of this test IP, which is every bit as valuable as design IP as it can be reused, enhanced, and extended, to add value throughout the product lifecycle. Full article    (PDF, 1.5 MB)

XJTAG yields success for Prism
Components in Electronics – July 2007

High-I/O package styles are successfully shrinking board dimensions, but are increasing the challenges surrounding test engineering. Boundary scan testing can offer a solution, and the latest equipment is able to deliver further savings in test development time by using a high-level programming language and supporting valuable test re-use. Full article    (PDF, 560k)

Made in the UK – Electronics Weekly – June 2007

The view that manufacturing to lower-cost services based offshore may be true for mass-market products, but production of high-value, advanced technology products is actually growing in the UK. To continue this success and deliver value at a competitive price, UK-based manufacturers must invest strategically and apply creative techniques at the design, assembly and test engineering stages. Full article    (PDF, 1.64 MB)

Boundary Scan Test is a must for designers using FPGAs and CPLDs – New Electronics – March 2007

Reconfigurable components such as FPGAs give engineers greater flexibility to update designs quickly and to deliver new products to an aggressive roadmap. But there can be untested hardware faults in circuitry that is not used until the upgrade is applied. Engineers need fast and effective techniques to test this dormant hardware.

With the prices of FPGAs, CPLDs and MCUs falling, it is becoming common for engineers to implement new features by reprogramming existing hardware or by updating software, bypassing the redesign of fundamental hardware. Upgrading by reprogramming also allows engineers to respond quickly to emerging standards, as is common in mobile communications. It can also ease customisation of designs to meet individual customer requirements. Full article    (PDF, 290k)

Boundary Scan Test for FPGA-Based Embedded Design – ESE – March 2007

System features integrated into modern FPGAs allow designers to implement an increasing proportion of an embedded design in a small number of reconfigurable components. It is quite normal to take advantage of the FPGA’s reconfigurability to download test programs to exercise various parts of the system and to perform self-test routines in the field. During development and prototyping, however, engineers must debug hardware before functional tests are ready. But the presence of the system features that are so valuable to the end product increasingly rules out the use of conventional probe-based test techniques. Full article    (PDF, 415k)

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