JTAG Boundary Scan Test Systems (IEEE 1149.1)

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Which CAD Netlist formats can XJTAG import?

XJTAG supports a wide range of netlist formats that the system automatically parses, identifies and accepts. You should be able to use any ASCII netlist; however if your netlist is not recognised, please contact XJTAG Support and we will be happy to convert it to a format that works and add a parser to a future release.

More about netlist formats on the XJTAG Blog.

I'm having problems with a Protel-generated EDIF netlist.

Some versions of Protel generate invalid EDIF netlists if hierarchical designs are processed. The problem is that empty cells which have not been defined are referenced in the netlist. To overcome this, we have added the option IGNORE_MISSING_CELLS to the NETLIST statement used in the board description file.

For example, if your code contains the following line:

NETLIST := "myNetlist.net", EDIF;

add the IGNORE_MISSING_CELLS option, thus:

NETLIST := "myNetlist.net", EDIF (IGNORE_MISSING_CELLS:=YES);

I'm having problems with a OrCAD Capture-generated EDIF netlist.

Some versions of OrCAD Capture generate invalid EDIF netlists:

• Bus names which traverse ports do not use a range starting or ending with the index "0". For example, if you use a bus named A[1..12], the generated netlist will correctly declare an array of twelve signals, but will attempt to reference some elements using an invalid array index. This will generate an error such as "Port index X not found in array YYYYYY" when XJTAG attempts to parse the netlist.
  Workaround: Either download the latest version of OrCAD Capture or set the "Output buses as scalars" option in the OrCAD Capture "Tools/Create Netlist" dialog. This will prevent buses from being exported as arrays in the EDIF file.
• Pins on a bus containing hash symbols are not renamed correctly. EDIF does not allow hash (#) symbols in net and port names, but OrCAD Capture can leave these in.
  Workaround: Export all buses as scalars.
• Sometimes GND connections aren't connected in the EDIF file.
  Workaround: Create a RINF netlist instead. Click on "Tools->Create Netlist...", click on the "Other" tab and select "rinf.dll".

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  Not only will XJTAG help to reduce our test NRE expenses, but it will enable us to significantly improve our diagnosis times and test coverage on densely packed circuit boards which are increasingly populated with flip chips, ball grid array and chip scale devices. ’
  
  Tim Murrell, Senior Electronics Engineer, PartnerTech
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