JTAG Boundary Scan Test Systems (IEEE 1149.1)

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Xilinx FPGAs

When running JTAG tests on a configured device, the pins may behave differently from an unconfigured device. For details of how to edit the BSDL file to reflect this, click here.

Virtex-II Pro

TDO is open-drain and should be pulled up (from the VII Pro User Guide).

Spartan-XL

INIT pin (77) must be grounded for it to work with JTAG.

Motorola Dragonball MC9328MX1

The BSDL file for this chip wrongly has prefixes for the pin names, which can be removed by one of the supplied Perl scripts. For more information, see the XJTAG help files.

National Semiconductor/AMD Geode

Some of the Geode BSDL files have syntax errors. Contact AMD and ask for a correct BSDL file, or contact us and we may be able to fix the BSDL file for you.

Marvell 10/100/1000 PHY (88E1111)

This device has been known to have faulty BSDL files. Contact your distributors and ask for a correct BSDL file, or contact us and we may be able to fix the BSDL file for you.

Altera FPGAs

Some Altera FPGAs appear to change their JTAG behaviour once they have been configured, so that the BSDL file no longer reflects the behaviour seen. This may cause problems with running tests, so make sure that the FPGA is not configured during testing.

Texas Instruments devices

Texas Instruments have a large range of JTAG-enabled devices. To use some of these devices, a few special considerations are required. These are detailed in an application note.

Configured Xilinx and Altera devices

If you are working with configured FPGAs and CPLDs, XJTAG can report errors that do not exist on your board. This application note explains why these errors are diagnosed and what you can do to resolve this problem.

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