JTAG Boundary Scan Test Systems (IEEE 1149.1)

Free XJTAG Boundary Scan Workshops

The full-day sessions are designed to provide design, development, test, and production engineers with a practical hands-on introduction to boundary scan.

Introduction to JTAG –
Concepts, Tools & Design for Test (DFT)

Find out how boundary scan can be used right across the product lifecycle to improve designs, reduce respins and enhance test coverage, fault diagnosis and production yields on complex BGA-populated circuits. The next workshop outlines the following:

  • Overview of the IEEE 1149.x standards
  • How to communicate with the JTAG chain
  • Tools to interact with JTAG devices, such as FPGAs or BGAs
  • Introduction to board testing using the JTAG chain
  • How to describe a circuit in order to enable JTAG testing
  • Fault finding abilities of a JTAG connection test
  • How to test non-JTAG elements of a board design using boundary scan

To book your place, please fill in the following form.  (Places subject to availability and at the discretion of XJTAG.)

Please complete all fields.


Given name: 
Family name: 
Email address: 
Telephone Number:

*We will contact you to confirm your booking shortly.

Boundary scan training worldwide

Date Venue Location Country  
19 May 2015 (Tuesday) XJTAG Headquarters Cambridge UK  
23 June 2015 (Tuesday) FlowCAD Zurich / Mägenwil Switzerland More info
25 June 2015 (Thursday) FlowCAD Munich / Feldkirchen Germany More info