JTAG Boundary Scan Test Systems (IEEE 1149.1)

The full-day sessions are designed to provide design, development, test, and production engineers with a practical hands-on introduction to boundary scan.

Find out how boundary scan can be used right across the product lifecycle to improve designs, reduce respins and enhance test coverage, fault diagnosis and production yields on complex BGA-populated circuits. The workshops outline the following:

• Overview of the IEEE 1149.x standards
• How to communicate with the JTAG chain
• Tools to interact with JTAG devices, such as FPGAs or BGAs
• Introduction to board testing using the JTAG chain
• How to describe a circuit in order to enable JTAG testing
• Fault finding abilities of a JTAG connection test
• How to test non-JTAG elements of a board design using boundary scan

Venue: XJTAG's headquarters in Cambridge, UK. Free lunch provided.

To book your place, please fill in the following form.

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