Changing the Connection Test Fault Coverage

The XJTAG connection test is an automated interconnect test that checks for shorts, opens, stuck-high, and stuck-low errors on a circuit board. Some PCBs have crosstalk or similar problems that, although possibly not affecting the normal running of the board, may cause issues during the XJTAG connection test. To handle such boards, there are several debug options that change how the connection test runs.

They are set in XJDeveloper’s XJRunner Setup screen in the Connection Test tab:

Setting up Connection Test options

Figure 1 – Setting the Connection Test Options

Maximum Number of Nets

This limits the number of nets that can change value simultaneously, helping to prevent ground bounce during the test.

Indirect Shorts

Part of the connection test is to check for shorts on the far side of resistors connected to JTAG devices.

If this “Indirect Shorts” testing causes spurious errors, selecting the “Reduced Sensitivity” radio button can help by limiting that test to only those nets that have connections defined in the Connections screen or are linked via passive devices.

To test all nets for indirect shorts (the default setting), select the “Full Indirect Short Testing” radio button.

One Way Indirect Shorts

This controls whether the connection test will test for shorts that occur through a buffer and resistor. By default, such errors are ignored because floating nets may mimic this type of error.

Remove the tick from the Ignore these errors checkbox to enable testing for shorts via a buffer and resistor.

Logic Testing

When this option is enabled (the default setting), XJTAG will test the operation of those logic blocks in the circuit that can be fully controlled and monitored by JTAG (or from external hardware if that is in use and enabled). It will check that they are operating as expected and that they are not causing any unexpected changes to other nets.

If the circuit has a very complicated combination of logic gates that is stopping the connection test from running, it can be helpful to disable logic testing while the connection test is being debugged. Logic testing is disabled by removing the tick from the Enable Logic Testing checkbox, but it should only be used as a temporary measure.

1149.6 Testing

When the Enable 1149.6 Testing option is set, it enables automatic 1149.6 testing where the JTAG devices support it.

Other settings related to 1149.6 testing should only be changed under guidance from XJTAG Support.

Inter-board Short Circuits

On large multi-board systems, test time can be reduced by not checking for shorts from those nets wholly contained on one board to those wholly contained on another. To disable such inter-board tests, remove the tick from the Check for Interboard short circuits checkbox in the Multiboard performance section.

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