Often, when designing a JTAG compatible device, the developer creates a RESET signal (or another type of initialisation signal) to reset the device’s JTAG boundary scan circuits. This/these pin(s) must be kept in a specified state for the device to meet the IEEE 1149.1 standard (JTAG), and it is this sort of pin that is often overlooked when designing RESET circuitry.
For example, many FPGAs have PROGRAM pins which, when pulled low, reset the boundary scan circuitry. Then the device will not be recognised in the JTAG chain, effectively ‘breaking the chain’. When there are two JTAG devices, one controlling the other’s compliance pattern, it should be checked that the default (reset) state is such that the compliance pattern is correctly set.