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Prototype to Production: Power Your AI Development with Hardware That Gives You Test Access and BSDL Support

Image of CEO of XJTAG Simon Payne Simon Payne, CEO, XJTAG |  Subscribe to LinkedIn newsletter

Every engineer pushing the limits of hardware feels the same demands: more performance and increased board density causing far less test visibility. You can’t test what you can’t reach, yet you’re still expected to guarantee reliability.

If you’re evaluating AI chips or modules for your hardware design, you’re not just buying performance, you’re investing in reliability from day one.

The best designs don’t wait until manufacturing to think about testability. They start at the prototype stage, using the right tools and verified data to prevent costly surprises later.

When an AI board fails, it’s rarely the chip that’s at fault. It’s almost always a connection that was never properly tested.

Why Great Designs Still Fail in Test

Not all AI chips or modules are equal when it comes to test access.

Some semiconductor vendors fail to provide a verified BSDL (Boundary-Scan Description Language) file, a prerequisite for enabling full boundary-scan (JTAG) testing.

This leaves engineers unable to validate solder joints, I/O connectivity, or board integrity after assembly.

Once the PCBA (Printed Circuit Board Assembly) is completed, the AI BGA (Ball Grid Array) device hides thousands of I/O pins beneath each device. There’s simply no physical way to check whether every BGA connection is sound, making structural test methods like boundary-scan essential for uncovering hidden defects.

You might be thinking, “We already use X-ray for that.” And you should, it’s a great tool. X-ray systems provide visual inspection that can reveal solder and assembly defects, but they cannot perform any electrical tests to verify signal connectivity or logic behavior and that’s where boundary-scan makes all the difference.

When Vendors Remove Your Safety Net

Some semiconductor vendors still don’t provide a verified BSDL file for JTAG boundary-scan testing of BGA devices, assuming that engineering teams will rely solely on functional testing.

There are two major issues with this assumption:

  1. Undetected faults: Functional tests can pass boards that actually have hidden faults. Cold solder joints, marginal opens, and partial connections can appear “good” at speed because of capacitance effects. These faults often worsen over time, leading to intermittent or early-life failures that are very expensive to diagnose and fix later.
  2. Limited fault insight: When functional tests do detect that something’s wrong, they rarely reveal what the fault is or where it’s located without considerable extra development time.

What You Lose When You Lose Boundary-Scan

Engineers rarely miss deliveries because of workload, they miss them because they can’t see what’s really happening in their circuit. When you’re chasing down a fault on a new board, it’s like working in the dark. Signals vanish under BGAs, nets disappear into inner layers, and every test feels like guesswork.

That lack of visibility costs time, rework, and ultimately deadlines. Verified BSDL files with the right tools change that – they let you see what’s going on even where your probes can’t reach, turning blind debugging into confident validation.

Selecting a device without a verified BSDL file and full boundary-scan capability means you and your colleagues in design and manufacturing lose a powerful tool for diagnosing board-level faults.

Without boundary-scan, fault isolation slows down, test coverage shrinks, and production debug costs escalate very quickly.

If your design includes BGA devices – as nearly all AI chips do – the thousands of buried I/O pins make physical access virtually impossible.

Engineers don’t need to be blind to what is happening beneath complex devices; boundary-scan brings those hidden faults into the light, exposing what’s really going on deep inside the PCBA.

What to Look For

Before selecting an AI chip or module, confirm the vendor provides a verified BSDL file, the foundation for implementing full boundary-scan testing.

A verified BSDL ensures compliance with the IEEE 1149.x standard and enables boundary-scan testing that provides interconnect verification between JTAG and non-JTAG devices on your PCBA. This unlocks broader fault coverage and diagnostic capability.

Boundary-scan operates at low speed, and that’s exactly why it works so well. By testing static interconnections and device pins, it reveals faults that high-speed functional tests often mask.

This ensures your engineers can:

  • Detect shorts, opens, and stuck-at faults
  • Validate soldering and interconnects across digital device pins, even under BGAs
  • Integrate boundary-scan with functional testing for complete coverage
  • Avoid costly rework and reduce early-life field failures

Boundary-scan doesn’t replace functional testing – it complements it. Together, they provide a full lifecycle safety net from prototype to production.

The Question that Separates Smart from Lucky

When comparing AI chips, don’t just focus on FLOPS, power, or price. Ask the question that separates reliable suppliers from risky ones:

“Does this AI device include a verified BSDL file to enable full boundary-scan testing?”

That single question could save your design and manufacturing teams weeks of debugging, cut thousands in support costs, and strengthen your product’s long-term reliability.

Design teams have told us that boundary-scan has transformed the way they approach debugging and validation. Instead of spending days chasing elusive faults, engineers now pinpoint issues in minutes, freeing valuable development time and reducing project delays. One team explained that the technology “enabled us to shave weeks off the development schedule by freeing our team from time-consuming debugging tasks.”

For many, boundary-scan has become “an absolute necessity for any company designing complex circuits with high pin-count devices.” It allows faults to be detected early, even on dense BGAs and buried nets where traditional probing methods fall short. By providing clear visibility and rapid diagnostics, it “helps us quickly localize any problems, saving time and simplifying rework.”

Across different industries and product types, the message is consistent: boundary-scan has become an essential tool for accelerating development, improving quality, and giving engineers the confidence that every board has been thoroughly tested before it leaves the bench or production line.

Take the Next Step

Before you finalize your next design, see how boundary-scan strengthens testing and reliability.

Explore more than 100 real-world examples where boundary-scan testing caught faults early, before production even began. View case studies

You can even try boundary-scan for free with your own board a quick way to see the faults your functional tests may have missed.

Final Note

Boundary-scan isn’t just a testing option, it’s a design decision that shapes every stage of your product’s journey, from the first prototype to full-scale manufacture.

By integrating boundary-scan early, not only do you strengthen your product’s long-term reliability and manufacturability, you strengthen your reputation.

Remember, the most effective testing strategy is a comprehensive one that combines multiple, complementary test methods to maximize fault coverage and confidence.

Whether you’re developing AI hardware, SoCs, FPGAs, or any other complex electronics, ensuring your key components are supported by verified BSDL files will deliver measurable benefits throughout the entire lifecycle – from design validation to field performance and customer satisfaction.

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“It’s Only a Small Board Change…” What Could Possibly Go Wrong? We recently spoke to an engineer about a new revision of an existing PCB. The message was: “It’s only an iterative change.” The implication was understandable: the design changes are small, so the additional test work should also be small. And they may be absolutely right. But it raises an important question: How do you know? A small PCB revision does not automatically mean a small test impact. How Much Test Work Does a Small PCB Revision Really Create? The answer depends less on how many things changed and more on what those changes affect. A reset signal may have moved. A buffer may have been added. A memory device may have been replaced. A previously unused FPGA pin may now be connected. A power rail or enable sequence may have changed. Each change may be small on the schematic, but if an existing test depends on it, the impact can be much greater. Every test makes assumptions about the hardware: which devices are fitted, how signals are connected, what can be controlled and observed, and how devices behave during test. Change one of those assumptions and the existing test may need to change too. What If the Change Is at the Centre of the Board? Now consider replacing the FPGA or processor at the heart of the design. Perhaps the new device performs essentially the same function and most of the surrounding circuitry is unchanged. It may look like a straightforward substitution. But that device may interact with a significant proportion of the board and therefore affect many existing tests. For teams using Boundary Scan, there is another important consideration: Is the BSDL file correct for the exact device and package now fitted? Boundary Scan software relies on the BSDL file to describe the device's pins, Boundary Scan cells, instructions and test capability. So a change that appears on the design change list as: “FPGA changed from A to B” could potentially affect considerably more of the existing test strategy than the change list initially suggests. This is why test effort isn't proportional to the number of changes. It depends on how central those changes are to the tests already developed. Regression Testing Isn't Just for Software Software engineers are familiar with regression testing. A small code change doesn't mean rewriting the entire application, but it does mean understanding what else could have been affected. PCB test deserves the same approach. For every revision, ask: What changed? Which existing tests depend on it? Which assumptions are still valid? Which tests can remain unchanged? Which tests need modifying? Is any additional test coverage required? The objective isn't to assume everything has changed. It's to avoid assuming nothing has. Reuse Should Still Be the Goal Last week, we looked at the value of reusing tests developed during bring-up through production, repair and support. A new board revision shouldn't change that principle. Good reusable tests should make iterative development easier. The aim is to preserve everything that remains valid and concentrate engineering effort only on the tests affected by the new design. Reuse the test — but validate the assumptions behind it. That is far more efficient than designing a complete test strategy again for every PCB revision. Closing Thought “It’s only an iterative change” may be completely true. And the additional test-development work may genuinely be trivial. But that should be the conclusion of an impact review, not the assumption at the start of one. When the next PCB revision is released, ask: What changed? Which of our existing tests depend on those changes? Are the assumptions behind those tests still valid? Then preserve everything that still works. The objective isn't to design a complete test from scratch. It's to know which tests need changing — and why. Board Design Tip of the Week When documenting your next PCB revision, add one more item to the change list: Test impact. For each design change, consider whether it affects: Component functionality or pinout Signal routing or connectivity Resets, enables or mode settings Power rails or sequencing Interfaces and control signals Physical test access Programming or configuration Existing test assumptions And if Boundary Scan forms part of your test strategy, also check whether the change affects the BSDL/device model or JTAG architecture. A short review at this stage can prevent a “small change” from becoming an unexpected test-development problem when the revised boards arrive. Discover more about your board design with the Free XJTAG Layout Viewer. To get started find out how the Free XJTAG Layout Viewer can help you see on your board: Download your Free XJTAG Layout Viewer today
Don’t Throw Away the Tests That Got Your Prototype Working The first prototype arrives and the engineering team begins the process of proving the hardware. Connections are checked. Memories are exercised. Peripherals are tested. Problems are found, understood and fixed. Eventually, the board works. And then something slightly strange can happen. Much of the test capability that helped get it working is never used again. Bring-Up Creates More Than a Working Board During bring-up, engineers build up a significant amount of knowledge about the hardware. They learn how to initialise devices. They discover which signals need to be controlled. They find ways of checking memories and peripherals. They work out how to distinguish between a software problem and a hardware problem. Sometimes this knowledge becomes a formal test. Sometimes it is a small utility written by one engineer. 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Turn Engineering Knowledge into Something Repeatable There is an important difference between knowing how to test something and having a test that someone else can run. If an engineer manually performs a sequence of checks during bring-up, that knowledge may disappear when the project moves on. If the same procedure is documented and automated where practical, it becomes reusable. That means the effort invested during development can continue providing value. Instead of every new team starting again, the product carries some of its diagnostic knowledge with it. Boundary Scan Is Particularly Well Suited to Reuse Boundary Scan can be especially useful here because structural tests are based on the hardware and its connectivity rather than depending entirely on the final application software. A test created to verify connections between devices during bring-up can potentially verify those same connections during manufacturing. A test used to exercise a memory, peripheral or other accessible device may remain useful during fault diagnosis. The reason for running the test changes. The physical hardware being checked does not. That gives structural tests the potential to move with the product from development into production and later support. Don't Lose the Tests at Handover When a product moves from development into manufacturing, the handover typically includes things such as: Schematics PCB data BOMs Manufacturing information Firmware Programming files Test specifications It is worth asking whether the diagnostic capability developed during bring-up should be treated in exactly the same way. Which tests proved particularly useful? Which interfaces can be independently verified? Which procedures helped isolate previous faults? Which tools or scripts should be retained? If that knowledge stays with one engineer rather than moving with the product, its value can easily be lost. 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But when a functional test fails, the symptom can sometimes cover a large area of hardware. Structural testing provides a different layer of evidence. Boundary Scan can often verify inaccessible PCB connections independently of the application software and relate unexpected results back to the nets and devices involved. That can help answer an important question: Is this an assembly problem, and if so, where should we investigate first? Boundary Scan does not replace functional production testing. It complements it by providing another way to understand the hardware beneath the symptom. One Failed Board May Be Manageable If one board fails, spending an hour investigating it may not seem significant. But what happens when ten fail? Or fifty? Or when the same type of fault appears repeatedly? At that point, diagnostic time starts affecting manufacturing throughput. That is why the economics of production test aren't determined only by how quickly passing boards can be tested. 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Structural tests developed during prototype bring-up don't necessarily need to be discarded once the design is working. Tests that proved connectivity, memories, peripherals or interfaces during development may also provide useful coverage in production. That means the effort invested in understanding the first prototypes can potentially become part of the manufacturing test strategy. Instead of starting again, knowledge moves forward with the product. Closing Thought A string of passing boards doesn't really test your diagnostic strategy. The first failure does. That is when you discover whether your test simply detects a problem or actually helps the engineer understand it. And the difference between knowing: “This board failed.” and: “This is where you should start looking.” can determine whether the problem is diagnosed in minutes, investigated for hours or placed on a growing bone pile marked: Investigate later. The best production tests don't just catch faults. They help engineers understand them. Board Design Tip of the Week Before releasing your next design, choose three realistic manufacturing faults. For example: An open connection beneath a BGA A short between two adjacent signals An incorrectly fitted peripheral Then ask: “If this happened on the production line, what would our test actually tell us?” If the answer is simply: FAIL there may still be work to do. Discover more about your board design with the Free XJTAG Layout Viewer. To get started find out how the Free XJTAG Layout Viewer can help you see on your board: Download your Free XJTAG Layout Viewer today