Why Probing an FPGA Board Is Often the Wrong First Instinct
When an FPGA doesn’t behave as expected, the instinct to probe is almost automatic.
Oscilloscope out. Logic analyser attached. Let’s see what’s going on.
But on FPGA boards, probing is often the least efficient first step.
Physical Access Has Changed
High-density packages, BGAs, and tightly coupled interfaces mean:
- Many critical signals are unreachable
- Others are sensitive to loading
- Some faults cannot be observed directly at all
Probing can confirm what you already suspect, but it rarely provides complete answers.
Probing Answers “What”, Not “Why”
Probes (if you have access) show signal behaviour, not intent.
They can tell you:
- A signal toggles
- A rail is present
- A clock exists
They don’t tell you:
- Whether every connection is correct
- Whether a pin is actually connected
- Whether the behaviour matches the design intent
That distinction matters during bring-up.
A More Useful First Question
Experienced FPGA engineers often pause and ask:
“What can I prove about this board before I chase behaviour?”
That shift, from observation to proof, saves time and reduces guesswork.
Closing Thought
Probing is still valuable. It’s just rarely the best starting point.
On complex FPGA boards, establishing confidence in connectivity and structure first often makes every subsequent debug step faster and more reliable.
FPGA Board-Level Tip of the Week
Treat the JTAG chain as a high-speed signal path, not a low-speed afterthought.
Although JTAG is often thought of as “slow control”, poor JTAG chain layout can create failures that block testing entirely, or worse, cause intermittent behaviour that’s hard to diagnose.
Why it matters
- JTAG clocks commonly run at 10–30 MHz, with some JTAG chains running significantly faster than this
- Noise, skew, and poor termination can corrupt scan data
- A marginal JTAG chain undermines all higher-level debug and test
What to watch out for
- Route TCK, TMS, TDI, and TDO consistently and avoid unnecessary stubs
- Do not tie nTRST directly to ground, this can disable the entire chain
- Correctly terminate TCK and TDO, this means adding more than just a pull resistor
A reliable JTAG chain doesn’t just enable testing, it creates confidence in every conclusion you draw from it.
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