How to Increase Boundary Scan Test Coverage

Simon Payne, CEO, XJTAG | Subscribe to LinkedIn newsletter

XJTAG Testing Times cartoon - Guilty as charged

Last week, we looked at how much of a PCB Boundary Scan can potentially test.

The answer can be surprisingly large.

A single processor, FPGA or SoC may provide access to memories, peripherals, interfaces and other circuitry far beyond the JTAG chain itself.

But the amount of useful test coverage you achieve isn’t determined by the semiconductor devices alone.

Many of the decisions made during schematic design can significantly increase how much of the finished board can ultimately be tested.

And in many cases, relatively small design choices can make a surprisingly large difference.

Start with the Boundary Scan Capability You Already Have

The first step is to understand the Boundary Scan capability provided by the major semiconductor devices in the design.

Processors, FPGAs, SoCs, CPLDs and many other devices may already provide control and observation of a large number of their digital pins.

Those pins effectively become potential test access points into the PCB.

Rather than simply asking:

“Which devices support JTAG?”

it is more useful to ask:

“What parts of the board can I reach through those devices?”

That shift in thinking is important because the useful reach of Boundary Scan can extend considerably beyond the devices in the JTAG chain.

Maximise Control and Observation

At the heart of structural testing are two simple capabilities:

Control can a signal be driven into a known state?

Observation can the resulting state be measured somewhere else?

The more opportunities a design provides for both, the greater the potential test coverage.

A connection between two Boundary Scan devices is an obvious example. One device may drive the signal while another observes it.

But the same principle can also extend into non-JTAG circuitry.

A Boundary Scan-enabled FPGA, for example, may provide the control signals needed to interact with a memory or peripheral, allowing a much larger section of the design to be tested.

Thinking about where signals can be controlled and observed during schematic design can therefore have a significant impact later.

Make Mode Pins Work for You

Configuration, boot and mode-selection pins are often treated as something that only needs to be correct for normal operation.

But providing some flexibility around these signals can considerably improve testability.

A device may need to be placed into a particular operating mode before an interface can be exercised.

If the required mode is permanently hard-wired, the options available during bring-up and test may be limited.

Providing resistor options or other suitable configuration choices, such as switches or off-board access to such signals, can allow engineers to select alternative modes when required.

These are often very inexpensive additions during design.

Once the PCB has been manufactured, however, the same flexibility can be difficult

to add.

Keep Resets and Enables Accessible

Resets and enables can have a disproportionate effect on test coverage.

Imagine an FPGA provides excellent Boundary Scan access to a peripheral.

If that peripheral is permanently held in reset until application software releases it, much of that potential test capability may be unavailable before the application runs.

Where appropriate, providing a means of controlling important resets and enable signals through accessible circuitry can make more of the board testable independently of the application.

The same applies to:

Buffers
Multiplexers
Level translators
Peripheral enables

Making these signals controllable can open test paths into much larger sections of the PCB.

When a watchdog circuit is present also make sure that it can be completely disabled to avoid problems with unexpected resets whilst running tests.

Think About Power Domains

Designs frequently contain multiple voltage rails and independently controlled power domains.

With a little planning, these don’t need to become barriers to testing.

Consider which devices need to be powered for a particular test and how those power domains are enabled.

Where level translators or isolation devices sit between domains, consider what state they will occupy during Boundary Scan testing and whether the relevant signals can still propagate.

The objective isn’t necessarily to power the entire product for every test.

In some cases, being able to deliberately bring up individual sections of the board can actually make testing more controlled and informative.

Design the JTAG Chain for the Product

The structure of the JTAG chain itself deserves consideration.

On a simple board, placing all Boundary Scan devices in a single chain may be entirely appropriate.

On a more complex system, several chains may offer advantages.

Separating devices can provide greater flexibility when different parts of the board are powered independently, when devices are optional, or when different areas of the product need to be accessed separately.

There is no universal JTAG architecture that suits every design.

The important thing is to make the decision deliberately, based on how the board will be developed, programmed, tested, manufactured and supported.

Use Boundary Scan Devices as Gateways

One of the most effective ways of increasing coverage is to stop thinking of Boundary Scan devices as the only things being tested.

Instead, think of them as gateways into the surrounding circuitry.

If an FPGA is connected to a memory, Boundary Scan access through the FPGA may allow that memory to be exercised.

If it connects to an ADC, it may be possible to read analogue measurements.

If it controls a DAC, known output values may be generated.

If it connects to an Ethernet PHY, the device may potentially be configured and its behaviour checked.

The Boundary Scan device provides the access.

The surrounding circuitry provides additional opportunities for testing.

This is how a relatively small number of JTAG-enabled devices can potentially provide visibility across a much larger proportion of the PCB.

Combine Boundary Scan with Other Test Methods

Increasing test coverage doesn’t mean trying to make Boundary Scan test absolutely everything.

Some parts of a design are naturally better suited to functional testing, measurement equipment or other test techniques.

The stronger approach is to understand what Boundary Scan can prove and use complementary methods for the remaining areas.

Boundary Scan might establish confidence in the underlying PCB connectivity.

Functional software can then prove that the completed system behaves correctly.

Oscilloscopes and other instrumentation can investigate areas where electrical measurements are required.

Each method contributes different information.

Together, they provide much greater confidence in the finished hardware.

Analyse Coverage Before the PCB Is Built

Perhaps the greatest opportunity to improve Boundary Scan coverage exists before layout is complete.

If testability is considered while the schematic is still being developed, engineers can identify areas where small changes could provide considerably greater access.

That might mean:

Making a reset controllable
Providing access to a mode pin or an important control signal
Changing the way a buffer is enabled
Reconsidering the JTAG chain architecture
Selecting a device with better Boundary Scan support

At this stage, these changes may be trivial.

After manufacture, they may require modifications or another PCB revision.

Designing for Greater Confidence

Throughout this series, we’ve repeatedly returned to the idea of building confidence in the hardware.

Increasing Boundary Scan coverage helps engineers establish that confidence across a greater proportion of the board.

More accessible signals mean more connections can be verified.

More controllable devices mean more circuitry can be exercised.

And greater coverage means fewer areas of uncertainty when the first prototype arrives.

Good testability doesn’t necessarily require major changes to the design.

Often, it simply requires asking the right questions early enough.

Closing Thought

The Boundary Scan capability inside your semiconductor devices is the starting point.

The PCB design determines how far that capability can reach.

By considering control, observation, mode selection, resets, power domains and JTAG architecture during design, engineers can significantly increase the amount of hardware that can be tested.

And the best time to create that additional visibility isn’t when a board has failed.

It’s while the schematic is still open in front of you.

Don’t Hand the Test Team a Finished Problem

It is easy to think of testing as something that happens after the hardware design is complete.

But by then, many of the decisions that determine what can and cannot be tested have already been made.

If test engineers are brought into the conversation earlier, relatively small design changes can provide significantly greater control, observation and diagnostic access.

That helps during the first board bring-up and gives the test team far more freedom when developing manufacturing tests later.

Rather than handing test engineers a finished board and asking them to find a way to test it, give them the access they need while there is still time to design it in.

That means thinking about testability as part o f the design process rather than something that is added one the design is completed.

Board Design Tip of the Week

During your next schematic review, pick one important non-JTAG device, perhaps a memory, peripheral or interface and work backwards from it.

Ask:

Can I control the signals it needs?

Can I observe enough of its behaviour to know whether it is working?

Can I put the surrounding circuitry into the state required to test it?

If the answer to any of those questions is no, look at whether a small design change could turn that part of the PCB into something you can test. It may be worthwhile making that change even if the additional access is not needed during normal operation, because it could provide valuable visibility during development, manufacturing test or fault diagnosis.

Sometimes a single resistor option, enable signal or accessible control pin can unlock considerably more Boundary Scan coverage.ould boundary scan make your next board easier to test?