SAN JOSE, CA, USA, Nov. 8, 2016 – Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its OrCAD® Capture has been enhanced to now include XJTAG® DFT Assistant, an easy-to-use interface that significantly increases the design for test (DFT) and debug capabilities of the schematic capture and PCB design system. Developed by boundary-scan hardware and software tool supplier XJTAG, XJTAG DFT Assistant allows users to detect and correct JTAG errors at the design stage before the PCB is produced, preventing costly re-spins and project delays.
Increasing design automation requires an appreciation for the challenges incurred and complexities involved at every stage of product development. EDA tools targeting complete product design offer many benefits, including the ability to increase functionality through extensions and plug-ins.
With as many as 25 million new devices coming online every single day over the next five years, the Internet of Things will require an unprecedented improvement in manufacturing and testing efficiency.
Implementing a Design for Test approach when designing PCBs at the schematic capture stage can now be significantly assisted using an innovative and free software extension that adds design verification to Altium Designer.
Boundary scan chain integrity can be checked automatically on Altium’s Designer schematic capture and PCB layout software, using an extension from Cambridge-based XJTAG.
When discussing the JTAG protocol, most engineers immediately think of In-System Programming procedures. Indeed, there are numerous Microcontrollers (or FPGAs, CPLDs) that employ this protocol when it comes to their programming and such applications are widely spread throughout the industry. The fact is that this protocol can be also used for various other purposes which can strengthen your testing techniques. Boundary Scan Testing (sometimes called JTAG testing) methods can significantly help you improve the Test Coverage. This paper presents dedicated hardware and software tools which are focused on performing Boundary Scan Testing (BST). Furthermore, some basic principles of the 1149.1 standard are described.