XJTAG has developed a testing tool in collaboration with PCB EDA vendors Altium, Cadence, Mentor Graphics and Zuken. The result is DFT-Assistant, enabling early correction of ‘Design For Test’ errors before any hardware is produced.
JTAG is implemented in CPUs, programmable devices and the other ICs that typically form the heart of any electronic product; however, its potential is often overlooked. Until now, design tools didn’t include any way to verify the JTAG system at the design stage.
For the first time, engineering can validate proactively the test access to their designs from within their CAD application and before any hardware is produced, preventing costly respins and delays.
The JTAG standard defines an electrical and physical method for connecting JTAG-enabled devices on a PCB, or across multiple PCBs. However, the technology behind the interface differs significantly from a standard communications interface.
JTAG effectively turns every pin on the device into a virtual test point, accessed electronically, which is extremely useful for debugging a prototype board. These virtual test points, accessible without a dedicated test fixture, mean that even first prototypes can be tested using JTAG, on a bench or even by the manufacturer.
Many engineers think that JTAG is simply an interface for inserting breakpoints to debug the software running on a CPU. It may surprise them to learn that JTAG is included in many integrated devices that do not have a debug interface. While this includes FPGAs and CPUs, it also extends to memory, communication interfaces and even general logic devices.
JTAG is so prevalent that in the majority of designs there will be at least one JTAG device on a board, and even a single JTAG-compliant device can be enough to make significant test coverage possible. Boundary scan is not limited to testing JTAG-enabled devices, however ...
The Altium Designer PCB development environment has powerful features that help engineers manage their designs from schematic to product. Altium sought XJTAG’s expertise in boundary scan to extend Altium Designer with Design-For-Test features that enable designers to find and correct errors and harness boundary scan’s power to maximise testability.
SAN JOSE, CA, USA, Nov. 8, 2016 – Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its OrCAD® Capture has been enhanced to now include XJTAG® DFT Assistant, an easy-to-use interface that significantly increases the design for test (DFT) and debug capabilities of the schematic capture and PCB design system. Developed by boundary-scan hardware and software tool supplier XJTAG, XJTAG DFT Assistant allows users to detect and correct JTAG errors at the design stage before the PCB is produced, preventing costly re-spins and project delays.