Many engineers think that JTAG is simply an interface for inserting breakpoints to debug the software running on a CPU. It may surprise them to learn that JTAG is included in many integrated devices that do not have a debug interface. While this includes FPGAs and CPUs, it also extends to memory, communication interfaces and even general logic devices.
JTAG is so prevalent that in the majority of designs there will be at least one JTAG device on a board, and even a single JTAG-compliant device can be enough to make significant test coverage possible. Boundary scan is not limited to testing JTAG-enabled devices, however …
SAN JOSE, CA, USA, Nov. 8, 2016 – Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its OrCAD® Capture has been enhanced to now include XJTAG® DFT Assistant, an easy-to-use interface that significantly increases the design for test (DFT) and debug capabilities of the schematic capture and PCB design system. Developed by boundary-scan hardware and software tool supplier XJTAG, XJTAG DFT Assistant allows users to detect and correct JTAG errors at the design stage before the PCB is produced, preventing costly re-spins and project delays.
Increasing design automation requires an appreciation for the challenges incurred and complexities involved at every stage of product development. EDA tools targeting complete product design offer many benefits, including the ability to increase functionality through extensions and plug-ins.
With as many as 25 million new devices coming online every single day over the next five years, the Internet of Things will require an unprecedented improvement in manufacturing and testing efficiency.
Implementing a Design for Test approach when designing PCBs at the schematic capture stage can now be significantly assisted using an innovative and free software extension that adds design verification to Altium Designer.