Cadence announced that its OrCAD® Capture has been enhanced to now include XJTAG® DFT Assistant, an easy-to-use interface that significantly increases the design for test (DFT) and debug capabilities of the schematic capture and PCB design system. The software interface enables early detection and repair of circuit board errors at the design stage, before hardware is produced.
XJTAG announces extended capability to its high-speed In-System Programming (ISP) technology, XJFlash. For the first time, this brings the benefits of XJFlash to memory devices connected to the processor sub-system of dual ARM-Cortex-A9 based FPGAs, such as the industry’s leading Xilinx Zynq and Altera Cyclone V SoCs. Experience programming times as much as 20 times faster than existing solutions.
XJTAG officially launches the XJTAG DFT Assistant for Altium Designer. Developed by XJTAG, the free software extension for Altium Designer significantly increases the Design for Test capabilities of the unified schematic capture and PCB design system.
The XJTAG DFT Assistant for Altium Designer provides engineers with a free, easy to use extension to check if boundary scan chains are correctly connected and terminated at the schematic capture stage, long before the PCB is produced.
XJTAG announces the release of Version 3.4 of its Development System, which introduces major improvements in the visibility into complex systems during all phases of electronic product development and manufacture.
XJTAG will be previewing major new features of the XJTAG Development System in Hall A1, Booth 572, including Log File Viewer and Waveform Viewer.
Working in conjunction with XJTAG’s production test environment, XJRunner, Log File Viewer successfully bridges the gap between the design domain and the production test environment by allowing test engineers to capture vital fault diagnosis and convey it back to design teams, enabling effective improvements in the Design for Manufacture and Test (DFM&T) process.
XJTAG releases latest update to its software suite. The focus of this release is on increasing the flexibility of JTAG chain control to make it easier for engineers to access the full JTAG capabilities of their boards and so achieve maximum test coverage.