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U.S. TECH – August 2019
DDR Memory Connectivity Testing and Boundary Scan
With the complexity of electronic circuits continually growing and the increased use of BGA packages, ways to verify error-free assembly become ever more important. One option is boundary scan testing, which offers an automated method to check components are operational, correctly placed, and free from soldering faults, without the need to run any software on the board.
When JEDEC published standards for GDDR5 and DDR4 memories, they defined inbuilt test features that work with these systems to support rapid checking for assembly faults. Such methods can prevent many wasted hours by providing early detection of problems, and are as applicable to the first prototype boards as they are to mainline production.
The drive to support this style of in-circuit testing has continued into the latest GDDR6 specification, published at the end of 2018. Connectivity test methods are available for these memory devices, and similar checks can be performed on LPDDR4 and DDR3 components, which do not incorporate inbuilt test modes.
