Free ‘Design For Test’ (DFT) plugin to reduce board re-spins
The new XJTAG® DFT Assistant for Zuken® CR-8000® Design Gateway plugin will allow design engineers to identify and correct potential JTAG testability problems early in the design cycle. Because many IC packages are inaccessible for testing using physical probes, failure to provide JTAG test access to these chips could result in a board re-spin and an expensive project delay.
XJTAG DFT Assistant will help you validate the correct implementation of boundary scan chains*, as well as provide compliance to ‘Design For Test’ best practices. What’s more, JTAG compliance can also unlock a range of other benefits for your board, which include faster prototype debug and device programming, as well as faster and more cost-effective manufacturing testing.
* Designers are not required to understand the underlying JTAG boundary scan technology to be able to use the plugin.
XJTAG Chain Checker
After a quick 4-step board setup, the XJTAG Chain Checker feature will analyse the netlist and find a routable scan chain. It will also offer a unique DFT feature: checking that the TAP signals are correctly terminated.
XJTAG Chain Checker will identify potential errors and warnings found on JTAG chains, including:
- Connection errors if any of the JTAG Test Access Point (TAP) signals are connected to the wrong pin(s) on a JTAG-compliant IC.
- Termination warnings if any of the TAP signals are not terminated as recommended.
- Compliance pin errors if they are incorrectly pulled high or low, or are left floating.
XJTAG Access Viewer
The XJTAG DFT Assistant extension will also identify the extent of JTAG access across an entire schematic. This will be overlaid directly onto the schematic using the XJTAG Access Viewer feature, allowing you to understand your test coverage at an early stage in the design. You will be able to highlight the nets individually on the schematic by JTAG access, to show: read, write, power/ground and no access.
By visualising the extent of JTAG access, you will be able to easily see which components are accessible using boundary scan and where changes need to be made to extend test coverage further.
- Fully integrated into Zuken’s CR-8000 Design Gateway
- Easy assisted board setup to carry out a JTAG DFT analysis
- Automatic import of netlist from Zuken CR-8000
- Will include a JTAG Access Viewer that can overlay testable nets directly on the schematic diagram
- Analysis of results from the XJTAG Chain Checker tool will clearly identify potential errors in the chain(s)
- Will provide three categories of errors: connection, termination and compliance
- Testable nets will be shown using colour-coded connections
- Assisted categorisation of logic and passive devices, to extend scan chains
- Capability to export projects for further test development using XJDeveloper