- New easy to use Design For Test (DFT) tool
- Free to PADS Schematic Design users
- Avoid costly re-spins by catching errors at the design stage
- Find errors in the JTAG chain(s) and repair them before producing any hardware
- Harness the full power of boundary scan to improve testability
Cambridge, UK, March 14, 2017 – Developed by XJTAG®, the free software for PADS® Schematic Design will significantly increase the Design for Test and Debug capabilities of the schematic capture and PCB design environment.
Printed circuit boards (PCBs) are increasingly densely populated and access to pins under many packages, such as Ball Grid Array (BGA), is virtually impossible. JTAG was designed to solve the problem of access and so it is now vitally important to get the JTAG chain right at the design stage. Failure to identify and fix design errors at an early stage can result in a board re-spin and a costly delay to a project. XJTAG DFT Assistant helps validate correct JTAG chain connectivity, through full integration with the PADS schematic capture environment.
“PADS products now include the XJTAG DFT Assistant that provides engineers with a free, easy to use interface to check if JTAG chains are correctly connected and terminated at the schematic capture stage, long before the PCB is produced,” said Jim Martens, Product Marketing Manager, PADS Solutions Group. “By detecting and correcting these faults earlier, companies do save both time and money. This software is free for PADS users of VX.2.1 or higher and can be downloaded from www.xjtag.com/pads.”
The XJTAG DFT Assistant comprises of two key elements; the XJTAG Chain Checker, and the XJTAG Access Viewer.
XJTAG Chain Checker identifies common errors in a JTAG scan chain, such as incorrectly connected Test Access Ports (TAPs). A single connection error would inhibit an entire scan chain from working. XJTAG Chain Checker identifies connection errors and reports them to the developer during the design process. Incorrectly terminated TAPs are also identified.
XJTAG Access Viewer overlays the extent of boundary scan access onto the schematic diagram, allowing users to instantly see which components are accessible using boundary scan, and where test coverage could be further extended. Engineers can highlight the nets individually to show read, write, power/ground and the nets that don’t have any JTAG access on the schematic.
While the first prototype is being manufactured, XJTAG DFT Assistant allows engineers to export a preliminary XJTAG project from the PADS schematic capture environment to the XJTAG development software, where additional tests can be developed. These can then be used to test real hardware, as soon as it’s available. This provides a vital new capability to electronic engineers everywhere.
About Mentor Graphics (www.mentor.com)
Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design and manufacturing solutions, providing products, consulting services and award-winning support for the world’s most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues in the last fiscal year of approximately $1.28 billion. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: www.mentor.com
About XJTAG (www.xjtag.com)
XJTAG is a world leading supplier of JTAG boundary-scan hardware and software tools. The company focuses on innovative product development and high quality technical support. XJTAG products use IEEE Std.1149.x (JTAG boundary-scan) to enable engineers to debug, test and program electronic circuits quickly and easily. This can significantly shorten the electronic design, development and manufacturing processes. More information about the company, its products and its services is available at www.xjtag.com.