JTAG Boundary Scan Test Systems (IEEE 1149.1)

Glossary & Abbreviations

ADC
Analog-to-Digital Converter

AOI
Automated Optical Inspection

API
Application Programming Interface

ASIC
Application Specific Integrated Circuit

ATE
Automated Test Equipment

AXI
Automated X-Ray Inspection

BGA
Ball Grid Array

Boundary Scan
A method allowing you to observe and have complete control of the boundary pins of a JTAG compatible device via software control.

BSDL
Boundary Scan Description Language

BSR
Boundary Scan Register

BST
Boundary Scan Test

CAD
Computer Aided Design

CEM
Contract Electronic Manufacturer

COB
Chip on Board

COM
Component Object Model, a standard Windows programming interface

CPLD
Complex Programmable Logic Device

CPU
Central Processing Unit

CSP
Chip Scale Package

DDR SDRAM
Double Data Rate Synchronous Dynamic Random Access Memory

DFT
Design for Test(ability)

DIL
Dual In Line

DLL
Dynamic Link Library

DRAM
Dynamic Random Access Memory

DSP
Digital Signal Processor

DUT
Device Under Test

ECM
Electronic Contract Manufacturing

EDA
Electronic Design Automation

EDIF
Electronic Device Interchange Format

EMS
Electronic Manufacturing Services (see also ECM). Term used for companies that design, test, manufacture, distribute, and provide return/repair services to OEMs.

FBT
Functional Board Test

FCT
Functional Test

FIFO
First In - First Out

FPGA
Field Programmable Gate Array

FPT
Flying Probe Test

HSDL
Hierarchical Scan Description Language (complements BSDL)

I²C
Inter-Integrated Circuit (or "two-wire interface") is a multi-master serial single-ended computer bus

IC
Integrated Circuit

ICT
In-Circuit Test

IDC
Insulation-Displacement Connector

IEEE 1149.1
IEEE (Institute of Electrical and Electronics Engineers) Standard 1149.1-1990 "Test Access Port and Boundary Scan Architecture" (see www.ieee.org)

I/O
Input / Output

IP
Intellectual Property

ISP
In-System Programming – the technique of programming devices after they have been soldered into the circuit board

JEDEC
Joint Electron Device Engineering Council

JTAG
Joint Test Action Group (usually refers to IEEE 1149.1 standard compliance)

MCM
Multi Chip Module

μP
Microprocessor

MCU or µC
Microcontroller Unit

.NET
.NET Framework, a standard Windows programming interface

NTRST
Test Reset (Active low TAP Signal)

NVM
Non-Volatile Memory

OE
Output Enable

OEM
Original Equipment Manufacturer

PCB
Printed Circuit Board

PLD
Programmable Logic Device

PLL
Phase Locked Loop

QFP
Quad Flat Pack

RAM
Random Access Memory

SDRAM
Synchronous Dynamic Random Access Memory

SMT
Surface Mount Technology

SoC
System-on-Chip

SRAM
Static Random Access Memory

SSRAM
Synchronous Static Random Access Memory

STAPL
Standard Test and Programming Language (JAM)

SVF
Serial Vector Format

TAP
Test Access Port (the 4- or 5-wire interface to a boundary scan device)

TCK
Test Clock (TAP Signal)

TDI
Test Data Input (TAP signal)

TDO
Test Data Output (TAP Signal)

TMS
Test Mode Select (TAP Signal)

TRST
Test Reset (Active low TAP Signal)

UART
Universal Asynchronous Receiver/Transmitter

UUT
Unit Under Test (can refer to components, boards, modules or systems)

VHDL
VHSIC Hardware Description Language

VHSIC
Very High Speed Integrated Circuit

VI
Virtual Instrument – program written in National Instrument's LabVIEW™ or other programming languages, to create user-defined hybrid test systems

VLSI
Very Large Scale Integration

XJTAG
A suite of tools aiding the development and test of electronic systems


XJTAG Ltd. © Copyright 2012. All rights reserved. Part of IEEE 1149.1