JTAG Testing with XJTAG


With JTAG abstraction, reactive test pattern generation and a device centric philosophy, XJTAG represents the most exciting advance in testing for a decade.

Testing is vital throughout the lifecycle of a circuit and, since the emergence of BGA and other similar packaging technologies, the contribution of JTAG has propelled it to the forefront of testing technology.

XJTAG has been designed to harness the full power of JTAG, while abstracting the process of test system creation from the technical details of test implementation.

While traditional JTAG solutions can use the connections between JTAG devices to implement connection tests, circuits still contain a lot of non-JTAG devices, many of which utilise BGA packaging, which cannot be tested either physically or by JTAG.

By contrast, XJTAG can adapt the behaviour of its tests to reflect the current status of devices in the circuit. It is, therefore able to functionally test a higher proportion of non-JTAG devices.

The ability of XJTAG to test the integrity of connections and the functionality of a circuit far beyond its JTAG chain makes it an invaluable tool for testing any circuit containing one or more JTAG-enabled devices.

Building XJTAG testing systems does not require any knowledge of the underlying JTAG boundary scan technology. The device-centric philosophy on which XJTAG is based means that tests are written from the perspective of the device being tested, without reference to the circuit. This means that any engineer who can understand a device datasheet can create XJTAG tests.

The device-centric philosophy also has the advantage that a set of tests written for a device can be used at any time, in any circuit. XJTAG is supplied with a set of ‘device files’, containing tests, so it is possible to create a test system without having to write any test code at all.

XJTAG makes the process of circuit testing quicker, easier and more efficient from pre-design through to field support.


Before a circuit is designed it is important that the engineer is aware of Design For Test (DFT) principles. XJTAG’s Design and Test Guidelines help to ensure that the eventual design of a circuit will yield the highest possible test coverage for all devices whether or not they comply with the JTAG standard.

Design validation

The process of testing can begin before the first circuit board has been produced. As soon as a design is complete, its netlist can be used as the basis for an XJTAG test system. XJTAG can produce a design for test report with no hardware attached, to check that the circuit layout provides all of the connections required to implement the specified tests.

By checking the circuit layout for testability prior to production, it is possible to avoid the time and cost incurred in reworking the design of the circuit at a later stage.

Circuit testing

XJTAG testing can begin before the circuit (or even the whole JTAG chain) is fully populated; as soon as a JTAG chain of one or more devices is available, testing can begin.

By removing the necessity for all of the circuit to be populated before implementing an XJTAG test system, the design cycle can be shortened by beginning the testing process, and potentially identifying faults, at a much earlier stage. XJTAG’s device-centric philosophy also means that any work done in creating tests at an early stage will not be lost, but can easily be modified to form part of a more fully-featured test system later.

Whatever proportion of the circuit is populated, the process of testing is the same.

Connecting the test system to the circuit

Before circuit testing can begin it is first necessary to connect the test system to the circuit. The XJLink provides high-speed JTAG access from any computer with a USB interface.

As the XJLink contains all licensing information, XJTAG test systems can be moved quickly and easily from one location to another: for example from the lab, with a standard desktop PC, into the field with a laptop.

The flexibility offered by XJTAG is enhanced by the ability to configure the pin mapping between the XJLink and the circuit under test. Standard pin mappings such as Multiice™, Xilinx™ or Altera Byte Blaster™ can be selected; alternatively, the pin mapping can be set up to match other specific, non-standard, layouts.

The XJLink can also be supplied with a fully featured programmers’ API. This allows you to create your own JTAG-enabled applications using the XJTAG hardware interface.

JTAG chain validation

As soon as a circuit is available, the next phase of implementing the XJTAG testing system is to ensure the integrity of the JTAG chain. XJAnalyser is a powerful graphical tool designed to facilitate fast chain validation and circuit debug.

The process of setting up an XJAnalyser project is extremely quick and easy, as project configuration options are set up using a project setup wizard.

Having established the correct configuration for the circuit under test XJAnalyser checks the integrity of the JTAG chain to which it is attached by extracting the ID code from each device in that chain.

With a valid chain established XJAnalyser uses the ID codes extracted to identify the appropriate BSDL files from its library. The BSDL files describe the implementation of the JTAG standard on each device.

As XJAnalyser is a project-based tool, once a project has been created, it can be saved and reloaded as required.


Main chain window in XJAnalyser
Figure 1 – The main chain window in XJAnalyser


Figure 1 is a screen shot from XJAnalyser showing a JTAG chain consisting of two devices. One of these devices is normally packaged, the other is a BGA device.

The colours of the pins indicate their current values. XJAnalyser can set the values for output and bi-directional pins to high, low, fast oscillating and slow oscillating.

As seen in Figure 1, XJAnalyser can also display information about the pins in a circuit on a per-device basis (the pin list in the right hand pane) or about a selection of pins (the pin watch in the bottom pane). This enables direct access to specific information of interest.

Manufacturing validation

With the integrity of the JTAG chain verified, the next stage in the process of testing is to check for manufacturing faults.

Short circuit examples
Figure 2 – Short circuit examples

XJTAG’s Connection Test identifies manufacturing faults in three categories: short circuits, open circuits and stuck at faults. Its proprietary connection test algorithm has been designed to facilitate a high percentage of circuit coverage and fault reporting that identifies the exact nature and location of faults.

Figure 2 shows an example of a situation that causes a major problem for many JTAG connection tests. While a simple short circuit, such as that shown between nets C and D, can be identified, the inline resistors in nets A and B mean that the short circuit between those two nets would not be detected. The XJTAG connection test algorithm overcomes this problem.

Fault reporting is improved by XJTAG’s ability to react to the current state of the circuit under test. When an inconsistency is identified more tests are automatically generated to pinpoint the nature and location of that fault.

Functional testing of non-JTAG devices

Even the most effective connection test will not be able to test all of the connections in a circuit. The manner in which XJTAG’s test patterns are generated enables functional testing of a wide range of non-JTAG devices, extending the ability of JTAG to test areas of the circuit away from the JTAG chain.

In the representation of an XJTAG test system shown in Figure 3, the testing of non-JTAG devices is controlled by the ‘XJEase device files‘. These device files contain high-level test descriptions for each device being tested. They do not, however, contain any information relating to how those tests should be implemented in the particular circuit under test; this makes all tests developed re-usable both within and across projects.

The XJEngine is responsible for generating the test patterns that implement the device tests. What a test pattern has to achieve in terms of setting pin values is controlled by the device file, the information required to create a test pattern to fulfil that requirement comes from the project file.

XJTAG Test System

Figure 3 – XJTAG Test System

All of these test patterns are generated as the test system is running. This means that the XJEngine is able to feed the current status of devices in the circuit back to the controlling XJEase device test. This information is used to programmatically control the next test pattern that the XJEngine must generate.

The introduction of programmatic control and reactive test pattern generation to JTAG testing expands both the percentage of a circuit and the range of devices that can be tested. Consider a device that needs to be put into a particular mode to enable testing. With an XJTAG test system, the XJEase device test simply describes the pins that need to be driven for the device to enter the testable mode; the test then loops, reading the device state, until a value is read that indicates that the mode has been entered and the test can proceed. Tests for such a device are only made possible by XJTAG’s circuit interaction.

The multiple levels of abstraction in XJTAG mean that test systems can be developed very quickly.

The abstraction of device testing from circuit implementation, the core of XJTAG’s device centric philosophy, provides two significant benefits. Firstly, the process of test development is much easier: tests are created by simply describing the pins that need to be set and the values that should result. Secondly, all tests that are developed can be reused whenever that device is used in other circuits and any changes to a circuits netlist will require no reworking of the test system.

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