Boundary Scan Description Language (BSDL) is based on the syntax and grammar of VHDL and describes how the boundary scan architecture has been implemented in a component. Without a BSDL file, a manufacturer cannot describe their device as IEEE 1149.1 compliant.

These files are normally available for download from manufacturers’ websites free of charge (see list below).

Boundary scan test systems such as XJTAG use the information contained in a BSDL file to determine how to access a device in the JTAG chain. The file contains the following elements:

  • Logical Port Description: describes each connection to the device. Ports that can be used for boundary scan are described as ‘in’, ‘out’, ‘inout’ or ‘buffer’; those that cannot be used, such as power or analogue pins, are described with terms such as ‘POWER_NEG’ and ‘LINKAGE_OUT’ respectively (files created before the 2013 standard do not differentiate between the different types of non-boundary scan port but designates them all as ‘LINKAGE’). This section uses symbolic names for each port rather than pin numbers to allow it to be reused with different pinouts.
  • ID Code Declaration: describes the contents of the device’s ID register (if implemented), which provides information such as manufacturer, part number and silicon version. While the register is optional for IEEE 1149.1 and 1149.6 devices, it is mandatory for those compliant with IEEE 1149.7.
  • Device Package Pin Mapping: maps each port’s symbolic name to a physical pin and identifies any pins that are not connected.
  • Scan Port Identification (TAP): defines the JTAG pins (TMS, TCK etc.).
  • Instruction Register Description: provides the length of the instruction register and lists the binary opcodes that must be placed in the register to perform each boundary scan operation (the only opcode defined in IEEE 1149.1-2013 is the one for BYPASS).
  • Register Access Description: defines which register will be placed between TDI and TDO for each JTAG instruction.
  • Boundary Register Description: provides the size of the boundary scan register and describes the individual cells that it uses.
  • Component Conformance to IEEE 1149.6: provides information about any cells that support capacitively-coupled digital signals and are IEEE 1149.6 compliant.
  • Configuration Register Description (IEEE 1149.7): describes the device’s IEEE 1149.7 capabilities, including its performance class and available functions.

The IEEE 1149 Standards define a set of standard cells that can be used to make up the boundary scan register. However, the manufacturer has the option to create their own cell architectures, in which case they will provide additional information that describes the behaviour of their non-standard cell types.

If a device’s JTAG pins only comply with the IEEE standard when it is placed in a test mode, the BSDL file will provide the bit pattern that needs to be applied to the device’s Compliance pin(s) to set it to boundary scan mode.

A more in-depth description of BSDL files can be found on the BSDL & SVF file formats, functions and features page.

Download BSDL files for your JTAG components

When the link doesn’t point to a list of files, please search for “BSDL” – List updated on 25 March 2022.

More BSDL files can be downloaded from the following community maintained website, but please be aware that the files may not be up to date: BSDL Files Library for JTAG.
(please note that this website is not connected to XJTAG and XJTAG is not responsible for their content).

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