Design for Test (DFT) Guidelines


The following guidelines provide suggestions for improving the testability of circuits using XJTAG. These guidelines should not be taken as a set of rules. The potential advantages in terms of testability should be considered together with all other implications which they may have (e.g. functionality, device cost and board area).

It is assumed that readers of this document have a minimal familiarity with the IEEE standards 1149.1 and 1149.6.

Throughout this document the term ‘1149.x’ refers to the IEEE 1149.x (JTAG) boundary scan standards, ‘JTAG devices’ means devices that implement JTAG boundary scan and are fully compliant with these standards, while ‘non-JTAG devices’ are those that do not implement JTAG boundary scan.

Specify and use JTAG devices

Although XJTAG is capable of testing the nets between JTAG devices and non-JTAG devices, greater coverage will be obtained by using JTAG devices wherever possible. The more JTAG devices that are incorporated into a circuit the greater the number of nodes that can be fully exercised and tested.

The 1149.6 standard allows the testing of capacitively coupled high speed single ended or differential signals that cannot be tested using 1149.1. In order to use this functionality it is important to ensure that nets to be tested in this way have 1149.6 capable pin on each side of the coupling capacitor.

Check the BSDL files for JTAG devices

Compliance with the 1149.x standards requires that the device must have a BSDL (Boundary Scan Description Language) file. This file describes the device’s specific implementation of 1149.x. Ensure that this file is available (usually directly from the device manufacturer’s web-site) and that it has been fully validated (BSDL syntax checking is included as an integral part of XJTAG).

Ensure the 1149.x chains are correctly designed and laid out

JTAG devices can have individual connectors to provide access to the TAP signals; however they can also be connected in a ‘daisy chain’ format with the TDO signal from one device connected to the TDI of the next.

Ensure JTAG chains are correctly designed and laid out

The TCK, TMS and (optional) nTRST signals must be connected in parallel to all devices connected in a ‘daisy chain’ format. It is important that nTRST signals are not connected directly to ground as this would completely disable JTAG, not only for an individual device but for the complete scan chain.

If possible, route the TAP signals away from other active signals to reduce noise and improve signal integrity. The serial JTAG interface will typically run with a clock rate of 10 MHz to 30 MHz, and poor layout can induce errors that are very difficult to pinpoint and can require a board re-spin to fix.

Interleaving TAP signals with power or ground can help diagnose problems with non-functioning JTAG chains; a TAP signal shorted to a constant signal is much more easily diagnosed than two TAP pins shorted together.

Use correct termination for all TAP signals

TCK should be terminated with a 68 Ω resistor and a 100 pF capacitor in series to ground, placed as close as possible to where the signal enters the final device in the chain. TDI and TMS should be pulled to the power rail with 10 kΩ resistors. TDO should be pulled to the power rail with a 10 kΩ resistor and have a 22 Ω series resistor fitted near to the final device in the chain. It is also recommended that a 10 kΩ pull-down resistor be added to the nTRST line to avoid floating inputs.

Use correct termination for all TAP signals

Multiple JTAG Chains

It may be necessary to have some devices directly connected to their own connectors for debug purposes during development or programming. Adding the option to link these connectors into a single chain for manufacturing test maybe beneficial and reduce both BOM (Bill of Materials) and handling costs during production. XJTAG’s XJLink2 controller can connect to up to four JTAG connectors on a board.

Connector design

JTAG Connector pinoutWhen specifying the signal positions on the JTAG connector it is important to consider possible crosstalk/interference issues. Interleaving active signals with ground connections will minimize these effects. If the number of pins available on the connector makes this impractical then prioritise placing TCK next to ground. If this is not possible then use a signal which is unlikely to change during JTAG scans such as reset, nTRST.

It is particularly important to avoid routing any TDO signal adjacent to TCK. TDO transitions occur on the falling edges of TCK; therefore cross-talk from TDO may cause a glitch on TCK, corrupting the data.

It is very important to have a strong ground connection between the JTAG controller and the board under test. If there are any spare pins on the JTAG connector to the board then adding extra ground signals will be beneficial. The XJLink2 has fixed ground connections on pins 10 and 20 so connecting these will improve signal integrity.

Ideally each new design will use the same connector type and signal layout so cables can be reused. These connectors should be ‘keyed’ to prevent misalignment.

If the connector can be accidentally fitted in reverse, then choose a pin layout that will prevent shorts between power pins to GND (or ‘soft GND’) pins of the TAP controller.

Routing the TAP signals to spare pins on other connectors may enable access to the scan chain even if the dedicated test access connector is unfitted or inaccessible.

JTAG mode select

On some devices TAP pins can be configured to have functions other than 1149.x boundary scan so it is important to ensure that the design does not prevent devices being used for JTAG testing. The function of these pins is normally configured by sampling other pins on the device as it is reset. Depending on the requirement of the design this configuration can be achieved in several ways:

  • If boundary scan is the only function required on the TAP pins the configuration pins can be tied to the required levels.
  • If boundary scan is the dominant function for the pins but it is possible that other functions may be required then optional fit resistors allow the configuration pins to be either high or low with a minor board change.
  • If there is a requirement to be able to switch easily between functions then the configuration signals can be brought out to a connector. Pull resistors can be used to define the default state which can then be overridden by a controller such as the XJLink2.

The EMU0 and EMU1 pins on a variety of Texas Instruments processors are one common example of such configuration pins while others include the Mode pins on Freescale processors and the JTAGSEL signal on the AT91 family of processors.

The required values for these pins will be defined in the datasheet/reference manual for the device; however they may also be shown in the COMPLIANCE_PATTERNS section of the BSDL file for the device.

Consider the clock to synchronous devices

Many synchronous devices can be tested by boundary scan however this will be dependant on the source of the clock. SDRAM, for example, can only be tested if the clock is controlled by an 1149.x compliant device. If a free-running clock were to be connected directly to the SDRAM then it would not be possible to synchronise the boundary scan test vectors to that clock in real time.

If a configurable JTAG device, such as a CPLD or FPGA, is available then route the clock source through that device to the SDRAM or clock buffers to maximize test coverage as shown below.

Clock to synchronous devices

It is also important to ensure that any clock buffers do not have a minimum operating frequency. Some clock buffers have a special control input to allow low frequency signals. Such signals must be accessible from a JTAG enabled pin.

Other devices, such as Ethernet PHYs and switches, require a specific frequency clock input in order to function. In these cases it is important to make sure the clock is not provided by an 1149.x enabled pin. A crystal or oscillator should be connected to the non-compliant device either directly or via a clock buffer.

While it will not be possible to use boundary scan to interact with the non-compliant device at these speeds; providing a suitable clock will often allow some level of testing that would not otherwise be possible.

Consider watchdog operation

Provide links or 1149.x controllable logic to ensure watchdog operation can be disabled during test. Reset events generated when a watchdog fails to receive a regular input during testing can produce unexpected test result or even prevent tests from completing.

Download the full DFT Guidelines eBook

Further points covered:

  • Test with unconfigured FPGAs and CPLDs
  • Ensure low skew between TAP signals
  • Provide access to help locate scan chain errors
  • Buffer the TAP signals and voltage level separation
  • Bypass optionally fitted 1149.x compliant devices
  • Include add-on and option boards in the 1149.x chain
  • If designing or specifying ASICs include 1149.x compliance
  • Make programmable parts accessible from the 1149.x chain
  • Provide direct access to programming signals
  • Surround logic clusters with JTAG devices
  • Extend 1149.x testing through connectors
  • Consider testing multi-board panels as one unit
  • Test analog circuits
  • Do not rely on programmable pull resistors
  • Consider using the functionality of JTAG devices
  • Use test functionality in non-JTAG devices
  • Interactive tests
  • Program non-volatile memory devices
  • Fast flash programming
  • JTAG glossary

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