High-level Guide to JTAG
JTAG is a technology that has existed for over a decade. However, its potential as a testing and programming tool is only just beginning to be fully realised.
Connection testing and In System Programming (ISP) are the two applications most commonly associated with JTAG. However the technology has far more to offer.
XJTAG, while not specifically referenced, harnesses the full power of JTAG and implements all of the functionality described in this document.
The technologies underpinning JTAG were developed in response to the difficulties encountered in testing circuits using the traditional 'bed-of-nails' approach. New packaging technologies such as BGA and Chip Scale Packaging has limited, and in some cases eliminated, physical access to pins.
|Figure 1 - Simple JTAG device|
With the effectiveness of traditional methods restricted, JTAG provides a method for accessing the values that would be on those pins. Figure 1 shows that, by using a JTAG cell placed between the pin and the internal logic of the device, JTAG can set and retrieve the values of pins without direct physical access.
The tester can decide whether they want to set and read the values going to and from the core logic or to and from the pins; there is also an option to just scan the values as they pass between the core logic and the pins during the normal operation of the device.
The JTAG interface requires four pins on each device, one to take data onto the device, one to take data off the device, one to control what is to be done with the data and one clock signal to synchronise the process.
For a device to be JTAG compliant its manufacturer must provide a BSDL (Boundary Scan Description Language) file, which describes how the JTAG aspects of the device work. The BSDL file is, in most cases, identifiable from an ID code that can be read out of the device using JTAG.
If a circuit contains more than one device that supports JTAG, they can be linked together to form a 'JTAG Chain'. In a JTAG chain the data output from the first device becomes the data input to the second device; the control and clock signals are common to all devices in the chain. Figure 2 provides a representation of a simple JTAG chain containing three devices.
|Figure 2 - Simple JTAG chain|
Ball Grid Array (BGA)
A BGA device, such as that shown in figure 3, differs from a normally packaged device in that all of its external connections are made through balls of solder between the bottom face of the device and the circuit board rather than through pins protruding from the side of the device.
The testing of circuits containing BGA devices has been one of the driving forces in popularising JTAG testing. With the connections between the device and the circuit board no longer accessible and visual inspection being equally affected, the only non-JTAG form of testing that can provide any form of useful information is X-ray inspection. This costly and time-consuming process requires that each board be X-rayed and the images inspected to check each solder ball has been correctly placed and the contact between the board and the device is intact but has not spread to cause short circuits. This process, while providing some information, still relies on visual inspection, whether manual or automated, and consequently cannot be fully relied upon to locate all errors.
Under these circumstances, JTAG connection testing has moved from being a useful alternative to bed-of-nails testing to a significant money saving tool that eliminates the need for costly X-ray technology.
Chain Integrity Testing
The most basic form of testing that can be conducted using JTAG is chain integrity testing, i.e. testing that the JTAG devices that are meant to be in the JTAG chain actually exist.
Each JTAG compliant device contains an ID code. By issuing the correct sequence of JTAG commands, the ID codes of all of the devices in the chain can be read out. A simple comparison of the actual IDs of the devices and the IDs returned from the JTAG chain provides a simple test that the devices are in place and that the JTAG chain is correctly connected.
The connection or interconnect test checks the interconnections between components in a circuit. These interconnections, know as nets, can have faults in three categories; short circuit, open circuit and stuck-at faults. Examples of these faults are shown in Figure 4.
Connection Test Example
A standard JTAG connection test can only check for faults on nets between JTAG devices, as these are the devices whose pin value can be set and read using JTAG. However, knowledge of the other, non-JTAG, devices in the circuit can allow for wider test coverage to areas of the circuit away from the JTAG chain.
A connection test is an invaluable tool in the process of manufacturing validation. Each circuit that is produced can be checked for production faults caused by manufacturing errors such as solder shorting connectors on a device. If a BGA device is considered, where there is little opportunity to visually inspect the connection, the full value of a fully-functional connection test can be realised.
Many modern programmable devices, such as FPGAs and CPLDs, are designed not only to be JTAG compliant, to facilitate testing such as that already described, but also with additional JTAG functionality to allow them to be programmed after they have been attached to the circuit.
Other devices, such as some flash memories, can be programmed indirectly through their connection to devices in the JTAG chain.
The ability to use JTAG to program devices 'in system' avoids the need to buy expensive programmers and socketed devices. There is also the advantage of being able to easily update the image held on the device.
Once the physical integrity of the circuit has been verified and devices appropriately programmed, functionality can also be tested.
Some JTAG-compliant devices are designed to incorporate a Built In Self Test (BIST) to test their internal logic. Applying the correct set of signals to the JTAG controller will cause these tests to be executed.
Other, non-JTAG-compliant, sections of a circuit can also be tested. This process is achieved using the interconnecting nets between the devices in the JTAG chain and other devices in the circuit.
This form of testing is often applied to a group, or cluster, of non-JTAG devices in the circuit. It works on the principle of setting the nets attached to the JTAG devices to pre-defined levels and then reading back a set of values and comparing them to those expected.
One variant of this method is memory testing. A sequence of JTAG test signals is created to manipulate the address and data busses of a memory device so as to write information into memory, a second set of test signals is created to read this information back.
Design for test
JTAG can be a valuable tool throughout the lifecycle of a circuit. There are elements of JTAG that can help designers, production test engineers and field test engineers.
However, the level of usefulness is dictated by the degree of coverage that a suite of JTAG tests is able to achieve. This is limited in part by the inherent characteristics of the circuit and in part by the way the designer has gone about the design.
A full set of Design For Test (DFT) guidelines is available from the XJTAG web site. However, most simply ensure that all JTAG compliant devices are properly connected and that an appropriate Test Access Port (TAP) has been designed into the circuit.
A low-level look at how JTAG is implemented
Suggestions for improving the testability of circuits
How XJTAG extends the possibilities of JTAG
Links to manufacturers' websites