Introduction to JTAG
JTAG is a technology that has existed for over a decade. However, its potential as a testing and programming tool is only just beginning to be fully realised.
Advances in silicon design such as increasing device density and, more recently, BGA packaging have reduced the efficacy of traditional testing methods.
In order to overcome these problems, some of the world's leading silicon manufacturers combined to form the Joint Test Action Group. The findings and recommendations of this group were used as the basis for the Institute of Electrical and Electronic Engineers (IEEE) standard 1149.1: Standard Test Access Port and Boundary Scan Architecture. This standard has retained its link to the group and is commonly known by the acronym JTAG.
For a device to be JTAG compliant, it must have an associated BSDL file which describes the implementation of JTAG in that device.
A platform-independent way of representing test sequences to be sent through the JTAG chain is SVF.
Non-JTAG-compliant sections of a circuit can be tested by using the interconnecting nets between the devices in the JTAG chain and other devices in the circuit.
See what JTAG can do
A low-level look at how JTAG is implemented
Suggestions for improving the testability of circuits
How XJTAG extends the possibilities of JTAG