Glossary & Abbreviations

Glossary

AC	Alternating Current
ADC	Analog-to-Digital Converter
AOI	Automated Optical Inspection
API	Application Programming Interface
ASIC	Application Specific Integrated Circuit
ATE	Automated Test Equipment
ATPG	Automatic Test Pattern Generation
AXI	Automated X-Ray Inspection
BGA	Ball Grid Array
Boundary Scan	A method allowing you to observe and have complete control of the boundary pins of a JTAG compatible device via software control.
BSDL	Boundary Scan Description Language
BSR	Boundary Scan Register
BST	Boundary Scan Test
CAD	Computer Aided Design
CEM	Contract Electronic Manufacturer. A firm that manufactures components or products for and based on the design of another hiring firm.
COB	Chip on Board
COM	Component Object Model, a standard Windows programming interface
Compliance Pin	A pin on a JTAG Compliant Device which must be held or sequenced to a particular state, as defined by the manufacturer, before the device will operate as a JTAG Compliant Device.
CPLD	Complex Programmable Logic Device
CPU	Central Processing Unit
CSP	Chip Scale Package
DC	Direct Current
DCE	Data Circuit-terminating Equipment
DDR SDRAM	Double Data Rate Synchronous Dynamic Random Access Memory
DFT	Design for Test / Design for Testability
DIL	Dual In-Line
DIP	Dual In-line Package
DLL	Dynamic Link Library
DRAM	Dynamic Random Access Memory
DSP	Digital Signal Processor
DTE	Data Terminal Equipment
DUT	Device Under Test
DVM	Digital Voltmeter
ECM	Electronic Contract Manufacturing
EDA	Electronic Design Automation
EDIF	Electronic Device Interchange Format
EEPROM	Electrically Erasable Programmable Read-Only Memory (same as E2PROM)
EMC	Electromagnetic compatibility
EMS	Electronic Manufacturing Services (see also ECM). Term used for companies that design, test, manufacture, distribute and provide return/repair services to OEMs.
FBT	Functional Board Test
FCT	Functional Test
FIFO	First In – First Out
FPGA	Field Programmable Gate Array
FPT	Flying Probe Test
HSDL	Hierarchical Scan Description Language (complements BSDL)
I²C	Inter-Integrated Circuit (or “two-wire interface”) is a multi-master serial single-ended computer bus
IC	Integrated Circuit
ICT	In-Circuit Test
IDC	Insulation-Displacement Connector
IEEE 1149.1	IEEE (Institute of Electrical and Electronics Engineers) Standard 1149.1-1990 “Test Access Port and Boundary Scan Architecture” (see www.ieee.org)
I/O	Input/Output
IP	Intellectual Property
ISP	In-System Programming – the technique of programming devices after they have been soldered into the circuit board
JEDEC	Joint Electron Device Engineering Council
JTAG	Joint Test Action Group (usually refers to IEEE 1149.1 standard compliance)
JTAG Chain	The serial connection of one or more JTAG Compliant Devices. The TDO from one device is linked to the TDI of the next device in order to form a single serial shift register across the chain of devices. TMS and TCK are connected in parallel to each device.
JTAG Compliant Device	An integrated circuit or device which implements Boundary Scan and complies with IEEE 1149.1
MCM	Multi Chip Module
MCU or µC	Microcontroller Unit
μP	Microprocessor
.NET	.NET Framework, a standard Windows programming interface
Netlist	A netlist is a text (ASCII) file that contains all the components and their electrical connections on a circuit board.
NRE	Non-Recurring Engineering
NTRST	Test Reset (Active low TAP Signal)
NVM	Non-Volatile Memory
OE	Output Enable
ODM	‘Original Design Manufacturer’ of a product which ultimately will be branded by another firm for sale
OEM	‘Original Equipment Manufacturer’ of a hardware component or sub-component.A company that sells products (including software) under its own label.
PCB	Printed Circuit Board
PGA	Pin Grid Array
PIO	Programmable Input/Output
PLCC	Plastic Leadless Chip Carrier
PLD	Programmable Logic Device
PLL	Phase Locked Loop
QFP	Quad Flat Pack
RAM	Random Access Memory
RS232	Recommended Standard 232 for serial binary single-ended data and control signals connecting between a DTE and a DCE
SMD	Surface Mount Device
SMT	Surface Mount Technology
SoC	System-on-Chip
SOIC	Small-Outline Integrated Circuit
SOJ	Small-Outline J-Lead
SRAM	Static Random Access Memory
SSRAM	Synchronous Static Random Access Memory
STAPL	Standard Test and Programming Language (JAM)
SVF	Serial Vector Format
TAP	Test Access Port (the 4- or 5-wire interface to a boundary scan device)
TCK	Test Clock (TAP Signal)
TDI	Test Data Input (TAP signal)
TDO	Test Data Output (TAP signal)
TMS	Test Mode Select (TAP signal)
TRST	Test Reset (Active low TAP signal)
TSOP	Thin Small-Outline Package
UART	Universal Asynchronous Receiver/Transmitter
UUT	Unit Under Test (can refer to components, boards, modules or systems)
VHDL	VHSIC Hardware Description Language
VHSIC	Very High Speed Integrated Circuit
VI	Virtual Instrument – program written in National Instrument’s LabVIEW™ or other programming languages, to create user-defined hybrid test systems
VLSI	Very Large Scale Integration
XJTAG	A suite of software and hardware products aiding the development and test of electronic systems